1. Field of the Invention
The present invention relates to a phase locked loop. The present invention relates to a semiconductor device including the phase locked loop.
2. Description of the Related Art
A phase locked loop (PLL) has functions of generating a periodic signal synchronized with a periodic signal input from the outside, and generating a periodic signal with cycles N times (N is a natural number) as much as a periodic signal input from the outside. Alternatively, the phase locked loop has a function of generating a stable periodic signal when a data signal which is similar to a periodic signal is input.
A basic configuration of a phase locked loop is disclosed in Patent Document 1.